VLSI testing methodology and testability design

Author: Lei Shaochong et al.
Publisher:
Publish Date: 2005-01-01
Features: This book systematically introduces the testing methodology and testability design of Very Large Scale Integration (VLSI), laying a solid foundation for readers to delve deeper into circuit design, simulation, testing, and analysis. It also establishes a platform for mutual exchange among circuit design, manufacturing, testing, and application at various levels (including circuit level, chip level, and system level). The main content of the book covers fundamental concepts and theories of circuit testing and analysis, description and simulation methods of digital circuits, test generation methods for combinational and sequential circuits, dedicated testability design, scan and boundary scan theory, IDDQ testing, principles of random and pseudorandom testing, various test generation circuit structures and their relationships with generated sequences, other test generation methods related to MY Deng Lie, built-in self-test principles, various data compression structures and their compression relationships, and testability design methods for dedicated circuits, memory, and SoC, among others. This book can serve as a reference for professionals in integrated circuit design, manufacturing, testing, application, EDA, and ATE, as well as a textbook for advanced undergraduate and graduate students in specialized courses.