Specialized Integrated Circuit

Author: Smith
Publisher:
Publish Date: 2004-01-01
Features: This book is a comprehensive and authoritative guide on Application-Specific Integrated Circuits (ASICs). It presents new methods for VLSI system design. The use of commercial tools and predesigned unit libraries has made ASIC design a faster, cheaper, and fewer errors approach to IC design, leading to its rapid adoption across various industrial applications. The book covers both semi-custom and programmable ASICs. After describing the fundamental principles of digital logic design and physical characteristics for each ASIC type, it discusses ASIC logic design input, logic synthesis, simulation, and testing, and further elaborates on the corresponding physical design—partitioning, floorplanning, layout, and routing. Additionally, the book provides a detailed explanation of all the knowledge and essential tasks required in ASIC design. It can serve as a textbook for senior undergraduate and graduate students and also as an ideal reference for engineering technicians in the ASIC field. The book targets a broad audience, serving as a textbook for undergraduates or graduates, as well as a reference for professionals in the industry working with ASICs. Another role of this book is to act as an "encyclopedia" for ASICs, minimizing the need for background knowledge while extensively using industry tools and examples. The examples in Chapters 2 and 3 utilize tools and libraries from MicroSim (PSpice), MetaSoftware (HSPICE), Compass Design Automation (standard cell and gate array libraries), and Tanner Research (L-Edit). The programmable ASIC design examples in Chapters 4–8 use tools from Compass, Synopsys, Actel, Altera, and Xilinx. The examples in Chapter 9 (involving low-end design input) employ tools from Exemplar, MINC, AMD, UC Berkeley, Compass, Capilano, Mentor Graphics, Corporation, and Cadence Design Systems. The VHDL examples in Chapter 10 have been verified using Mentor’s QuickVHDL, Model Technology’s V-SystemPlus, and Compass’s Scout. The Verilog examples in Chapter 11 have been tested with Cadence’s Verilog-XL, Wellspring Solutions’ V-SystemPlus, and VeriWell. The logic synthesis examples in Chapter 12 have been tested with Compass’s ASIC Compiler product line and tools from Mentor, Synopsys, and UC Berkeley. The simulation examples in Chapter 13 have been tested with Capilano Computing’s QuickVHDL, V-System/Plus, PSpice, Verilog-XL, DesignWorks, CompassSim, QSim, MixSim, and HSPICE. The testing examples in Chapter 14 have been verified using test software from Compass, Cadence, Mentor, Synopsys, and Capilano’s DesignWorks. The physical design examples in Chapters 15–17 have been generated and tested using Preview, Gate Ensemble, Cell Ensemble (Cadence), as well as ChipPlanner, ChipCompiler, and PathFinder (Compass). All these tools are installed at the University of Hawaii.