Write a test platform—Functional verification of HDL models (Second Edition)

Author: (USA) Bergeron, J. (Author), translated by Zhang Chun et al.
Publisher:
Publish Date: 2006-08-01
Features: Verification is a necessary step in manufacturing functionally correct chips and is a process that demonstrates how design ideas are implemented. This book first introduces the basic concepts and tools of verification, the importance and cost of verification, compares different verification methods, and distinguishes between testing and verification. Then, from a methodological perspective, it explores verification strategies and levels, introduces coverage models, and explains how to develop a comprehensive verification plan. In terms of verification methods and techniques, the book introduces Hardware Verification Languages (HVL), discusses high-level modeling using behavioral description, introduces techniques for applying stimuli and monitoring responses, and explains how to abstract physical-layer transactions into higher levels using bus functional models. It also covers various test languages and the key elements of simulation management. The book proposes a coverage-driven, constrained random transaction-level self-checking testbench and systematically discusses the principles and design elements of each component within this structure. It also introduces how to write self-checking testbenches and design random stimulus generators based on bus functional models. This book is suitable for professionals engaged in ASIC, SoC, and system design and verification.