Verilog HDL Synthesis Practical Tutorial

Author: J.Bhasker
Publisher:
Publish Date: 2004-11-01
Features: The distinctive feature of this book lies in helping readers comprehensively and correctly understand the synthesis of the Verilog hardware description language. With circuit synthesis as the goal, it discusses the synthesizability of various language structures, the semantic differences between simulation and synthesis, and related usage examples. It provides numerous examples, compares various ambiguous usages, points out their semantic differences, and highlights the functional differences of the circuits synthesized. Another distinctive feature of this book is the detailed introduction of optimization and verification techniques for design models. The content is comprehensive, easy to understand, and widely applicable. For students and engineers who have adopted or plan to adopt the Verilog language as a circuit design tool, this book is an invaluable resource.