VHDL Design, Representation, and Synthesis (English Version·Second Edition) (English Version·Second Edition)

Author: Armstrong
Publisher:
Publish Date: 2003-03-01
Features: This book clearly and comprehensively explains the mainstream methods of modern hardware design—using hardware description languages for synthesis—as well as the latest knowledge in mainstream synthesis tools. The two authoritative authors begin with an introduction to structured design, delve into the VHDL language and its key structures, and then gradually explain the modeling process using examples at various abstraction levels. They also discuss various techniques for improving simulation efficiency and synthesis tool compatibility.
Main Content
Design Tools: Editors, Simulators, Checkers, Analyzers, Optimizers, and Synthesizers
VHDL: Main Structures, Syntactic Descriptions, Source Files, Data Types, Data Objects, Statements, and Advanced Features
Basic VHDL Modeling Techniques: Transmission and Delay, Concurrency, Combinational Logic, Sequential Logic, System Primitives, etc.
Integrating VHDL with the Design Process: From algorithm-level executable specifications to gate-level or unit-level implementations
PLD, Gate Array, FPGA (using Xilinx tools), and Standard Cell (using Synopsys) Modeling