Verilog HDL Synthesis Practical Tutorial

Author: Basile
Publisher:
Publish Date: 2004-01-01
Features: Through this book, you can: · Quickly start writing synthesizable Verilog models. · Learn which language constructs are suitable for synthesis and how they map to hardware to achieve the desired logic circuit. · Learn how to avoid functional mismatches. · Start using many commonly used hardware component models immediately, or slightly modify them for your own use.
Reviews of the Book:
"This book is easy to read and provides a wealth of synthesizable Verilog model examples, offering a shortcut for students and logic design engineers to quickly master the knowledge of VerilogHDL synthesis." — Vassilios Gerousis, Senior Engineer at Motorola
"This book is an ideal textbook for teaching Verilog-based synthesis technology. It not only demonstrates the hardware resulting from various Verilog structures but also shows how to trim Verilog programs to achieve the desired hardware." — Jim Vellenga, Viewlogic Systems
"This book reveals the various scenarios where differences between simulation and synthesis are inevitable. Carefully selected cases make both beginners and experienced designers aware of these common pitfalls that are hard to detect during debugging but extremely prevalent." — Carlos Roman, Bell Labs
"This is an excellent guidebook that clearly and concisely explains how to design synthesizable RTL models." — Douglas J. Smith, author of "HDL Chip Design"
"This book is organized in an example-driven manner, making it highly valuable for Verilog beginners." — Egbert Molenkamp, University of Twente (Netherlands)
The distinctive feature of this book lies in helping readers fully and correctly understand the synthesis of the Verilog hardware description language. With the goal of circuit synthesis in mind, it discusses the synthesizability of various language constructs, the semantic differences between simulation and synthesis, and related usage scenarios, providing numerous examples. It contrasts various ambiguous usages, points out their semantic differences, and highlights the functional differences in the circuits synthesized. Another distinctive feature of this book is its detailed introduction to optimization and verification techniques for design models. The book is comprehensive, easy to understand, and widely applicable. For students and engineers who are already using or planning to use Verilog as a circuit design tool, it is an invaluable resource.