Hardware Design Verification: Based on Simulation and Formal Methods

Author: William K. Lam (USA)
Publisher:
Publish Date: 2007-01-01
Features: This book comprehensively introduces the techniques and methods of hardware system design verification, primarily focusing on simulation-based and formal verification methods. The content covers static verification, simulator architecture, testbench design, simulation planning and strategies, debugging processes and verification cycles, as well as background knowledge of formal verification, decision diagrams and SAT problems, symbolic computation, and model checking. The book compiles a wealth of fundamental concepts and techniques in design verification, presenting the material in an accessible yet detailed manner. It discusses general testing principles while also demonstrating practical methods, reflecting the author's extensive years of experience and making it highly practical. Each chapter is followed by various exercises to help readers reinforce their knowledge. This book is suitable as a textbook for senior undergraduate students or early graduate students in electronic science and technology, computer science and technology, and related fields, as well as a reference for engineers in related disciplines.
As digital logic design scales up in size and complexity, functional verification has become the primary bottleneck in the design process. Shortening verification time is key to project success. This book systematically elaborates on the most valuable simulation-based and formal verification techniques of today, helping test engineers and design engineers select the best solutions for each project, build confidence in their designs quickly, and transfer it to faster manufacturing processes. The author, William K. Lam, is a world-class expert in design verification, and the book gathers his extensive practical experience, discussing both general testing principles and specific implementation methods. Some sections even provide algorithms in pseudocode, which readers can easily adapt to specific programming languages for debugging. Whether you are a university student or a verification engineer in a company, you can benefit from this book.
This book comprehensively introduces the techniques and methods of hardware system design verification, primarily focusing on simulation-based and formal verification methods. The content covers static verification, simulator architecture, testbench design, simulation planning and strategies, debugging processes and verification cycles, as well as background knowledge of formal verification, decision diagrams and SAT problems, symbolic computation, and model checking. The book compiles a wealth of fundamental concepts and techniques in design verification, presenting the material in an accessible yet detailed manner. It discusses general testing principles while also demonstrating practical methods, reflecting the author's extensive years of experience and making it highly practical. Each chapter is followed by various exercises to help readers reinforce their knowledge. This book is suitable as a textbook for senior undergraduate students or early graduate students in electronic science and technology, computer science and technology, and related fields, as well as a reference for engineers in related disciplines.