SystemVerilog Assertions Application Guide

Author: Chen Junjie
Publisher:
Publish Date: 2006-10-01
Features: The writing style of this book enables engineers to quickly master SystemVerilog assertions. Chapters 0, 1, and 2 provide a thorough understanding of basic syntax and general simulation techniques. After reading these three chapters, readers should be able to write assertions in their design/validation environments. Chapters 3, 4, 5, and 6 are "cookbooks" for different types of designs. If readers encounter similar designs in their own environments, they can refer to these chapters as a starting point to write assertions. These chapters can also serve as guidelines. A CD is included with the book. All examples in this book can run with the VCS2005.06 release, along with script examples for running these examples. VCS is a registered trademark of Synopsys.