VHDL Design Representation and Synthesis (English Version. 2nd Edition) (with CD-ROM)

Author: James R Armstrong
Publisher:
Publication Date: 2003-03-01
Features: This book clearly and comprehensively explains the mainstream methods of modern hardware design—using hardware description languages for synthesis—and the latest knowledge in mainstream synthesis tools. The two authoritative authors begin with an introduction to structured design, delve into the VHDL language and its key structures, and then gradually explain the modeling process using examples at various levels of abstraction. They also elaborate on various techniques for improving simulation efficiency and synthesis tool compatibility. Main Content Design Tools: Editors, Simulators, Checkers, Analyzers, Optimizers, and Synthesizers VHDL: Main Structures, Syntactic Descriptions, Source Files, Data Types, Data Objects, Statements, and Advanced Features Basic VHDL Modeling Techniques: Transmission and Delay, Concurrency, Combinational Logic, Sequential Logic, System Primitives, etc. Integrating VHDL with the Design Process: From executable specifications at the algorithmic level to implementation at the gate-level or unit-level PLD, gate arrays, FPGA (using Xilinx tools), and standard cells (using Synopsys) modeling