Introduction to the Methodology of Ultra-Large-Scale Integrated Circuit Design

Author: Yang Zhilian / et al.
Editor-in-Chief: Wang Renkang
Publisher:
Publish Date: 1999-03-01
Features:
This book provides an overview of the integrated circuit design process and steps, systematically discusses various methods for designing integrated circuits, and explores the characteristics and applicable ranges of full-custom, custom, semi-custom, and programmable logic device and logic cell array design methods. It also covers the VHDL hardware description language and logic synthesis in high-level design. Detailed analysis is given on various computer simulation tools and their algorithms, including logic simulation, circuit simulation, device simulation, and process simulation. Additionally, the semiconductor device models in the SPICE circuit simulation program are introduced in detail. Finally, the book discusses layout editing and layout verification for integrated circuits. This book can serve as a textbook for undergraduate and graduate students in microelectronics and semiconductor programs, as well as a reference for integrated circuit chip designers and microelectronics engineering technicians.
Excerpt:
Since there may be multiple hardware structures to implement the design's functionality, the goal of high-level synthesis is to find the least-cost hardware structure that meets the objectives and constraints while optimizing the design's performance. Logic synthesis converts behavioral descriptions at the logic level into structural descriptions, such as logic gate netlists. Behavioral descriptions at the logic level can be state transition diagrams, finite state machines, Boolean equations, truth tables, or hardware description languages. The logic synthesis process also includes a series of optimization steps, such as resource sharing, connection optimization, and clock distribution. The optimization objectives are to minimize area, maximize speed, reduce power consumption, or achieve some trade-off between them. Generally, logic synthesis is divided into two stages: ① a technology-independent stage, where Boolean or algebraic operations are used to optimize logic; ② a technology mapping stage, where the design is mapped based on the circuit's nature (e.g., combinational or sequential) and the chosen structure (multi-level logic, PLD, or FPGA), converting the technology-independent description into a gate-level netlist or an executable file for PLD or FPGA. After logic synthesis optimization, detailed delay analysis and delay optimization are required. Additionally, logic simulation must be performed. Logic simulation is a critical step in ensuring design correctness. In the past, software simulation methods were commonly used, but in recent years, hardware simulation methods, such as simulation through PLDs or FPGAs, have been emphasized. Test synthesis provides automatic test pattern generation (ATPG), offering high fault coverage for test patterns in design for testability (DFT). Test synthesis can also eliminate redundant logic, diagnose untestable logic structures, and automatically insert testability structures. Physical synthesis, also known as layout synthesis, automates the conversion of a gate-level netlist into a layout, completing the placement and routing. The detailed steps of layout are shown in Figure 1-5. Layout planning (floorplan) involves physically partitioning the design and planning and analyzing its layout. In this step, the physical partitioning may differ from the logical design hierarchy. Layout planning can estimate more accurate interconnect delay information, budget chip area, and identify congested routing areas. Layout refers to placing modules in appropriate locations on the chip while meeting certain objective functions. General layout always aims to minimize chip area, shorten wire length, and optimize electrical performance while ensuring ease of routing. Layout is divided into two sub-steps: initial layout and iterative improvement. The purpose of initial layout is to improve layout quality and reduce the number of iterations in subsequent improvement steps, while iterative improvement is the process of optimizing the layout and is key to determining its quality. Routing, based on the connection relationship description (i.e., connection table), completes 100% of the required interconnects within the specified area (area, shape, hierarchy, etc.) while satisfying process rules and electrical performance requirements, and optimizes wire length and via count as much as possible. There are generally two routing methods: one is netlist-oriented routing, which directly routes the entire circuit, typically using a sequential approach; the other is hierarchical routing, which divides the routing problem into global routing and detailed routing. This is a routing area-oriented method that divides the entire routing area into several routing channels through appropriate partitioning, then allocates all endpoint paths of a net to the corresponding channels. Subsequently, detailed routing determines the specific positions of all routed segments within the channel according to certain rules. After layout and routing are completed, design rule checks, electrical rule checks, and layout-to-circuit consistency checks must be performed. Circuit analysis (i.e., back-simulation) is conducted again based on layout parasitic parameter extraction. Only after all checks pass and the design is proven correct can the layout results be converted into mask files. These mask files are then used to generate mask plates, typically through mask plate generators or electron beam lithography systems.
1.5 Impact of Deep Submicron Circuit Design on the Design Process
The silicon integrated circuit industry has now entered the mass production stage of 0.5μm feature size products, and 0.35μm technology has also entered pilot production. In 1994, the Semiconductor Industry Association (SIA) released a forecast for the development of integrated circuit technology from 1995 to 2010, as shown in Table 1-2. The first decade of the 21st century will face the challenge of designing and manufacturing circuits at the 0.1μm level. The transition from micro- and submicrometer to deep submicrometer technology has posed new challenges and issues for integrated circuit design and its methodologies. The first challenge is to establish accurate deep submicrometer device models, timing models, and interconnect models. A prominent contradiction in deep submicrometer circuit design is timing issues. At the deep submicrometer level, interconnect delay will exceed gate delay. Moreover, as the operating frequency of integrated circuits increases, the allowable timing tolerance decreases, and the impact of transmission delay becomes more significant, making circuit design more challenging. In micro-scale circuit design, it is customary to divide the design into two stages. The first stage is collectively referred to as logic design, where system and functional design, as well as structural and circuit design, are performed. The second stage is called layout design, primarily involving placement, routing, physical verification, and mask generation. Communication between the two stages is mainly through netlists and unit libraries. After front-end design is completed, the netlist is passed to the layout designer. Generally, as long as routing can be completed, timing requirements can also be met. However, in the deep submicrometer stage, the situation is different. If the front-end design does not fully consider the various issues of the back-end design, especially the timing issues that arise after physical implementation, the results of logic design and physical design may become inconsistent. A netlist that is functionally and timing-correct after simulation analysis in logic design may no longer meet timing requirements after actual placement and routing. This is because interconnect delay depends on the specific routing and plays a dominant role in the overall chip delay. Furthermore, the interconnect delay model used in logic design may not align with the actual interconnect delay characteristics, leading to timing that no longer meets design requirements. This necessitates revising the logic design and reperforming simulation analysis. If the logic design still cannot obtain accurate, real-world interconnect delay data, even after modifications, the physical design may still not meet requirements. This cycle can lead to "non-convergence" between logic and physical design, significantly extending the design cycle.